ZYNQ-7Z010 SOM B’d (Rev.A)

This ZYNQ SoC features ARM Cortex-A9 Dual Core as Processing System (PS) and FPGA Fabric (eqv. to Artix-7) as Programmable Logic (PL).
Basic system control is performed by the PS, while the PL is utilized for hardware acceleration when computational tasks require it.

2. DDR3L Memory

Micron’s two DDR3L Memory products (512MB) were used and connected in a fly-by-routing method to form a 1GB DDR Memory.

3. VTT Regulator

It is used to accurately track half of the memory supply voltage VDD while sourcing/sinking the current according to the high/low state of the DDR Memory Bus I/O.

4. PS Clock Oscillator

33.33 MHz Oscillator was used as a clock source required for ARM Cortex-A9 (PS) operation.

5. PL Clock Oscillator

50 MHz Oscillator was used as a clock source required for the operation of the FPGA Fabric (PL).

6. JTAG Connector Footprint

JTAG Connector Footprint was applied for ZYNQ’s program flash and debugging.

7. Edge Connector (DDR4 SODIMM FF)

Designing the ZYNQ SoC and peripheral circuits for each required system can incur time and financial costs. Therefore, we have adopted the Edge Connector method to allow for the reuse of the ZYNQ and peripheral circuits.

Schematic of ZYNQ-7Z010 SOM B’d (Rev.A)

PCB Artwork of ZYNQ-7Z010 SOM B’d (Rev.A)

1. PCB Stack-up based on JLCPCB Impedance Calculation

2. PCB Layers of ZYNQ-7Z010 SOM B’d (Rev.A)

3. Delay Matching of DDR Memory

Basic Verification of ZYNQ-7Z010 SOM B’d (Rev.A)

1. Check the JTAG Connection Status of the ZYNQ SOM Board

Power the FPGA / SoC B’d and Connect B’d to PC, and Execute Vivado IDE.

And run “Tasks – Open Hardware Manager” to verify that the HW connection is successful before create the project.

As follows, in the case of ZYNQ SOC, Both ZYNQ PS (ARM) and PL should be recognized correctly by Vivado.

2. Test the ARM Cortex-A9 On-chip Memory Read/Write

An additional method to verify the proper connection between the ZYNQ PS and Vivado IDE is to perform Read/Write operations on the OCM (On-Chip Memory) area of the ARM CPU Core.

Run the “xsdb.bat (Xilinx System Debugger)” located at the following path.

If you enter “help” in the console window, a list of available commands and their descriptions will appear.

Enter “connect” in the console window to connect to the target. This is equivalent to opening the Vivado Hardware Manager and selecting ‘auto connect target’.

This will launch the Hardware Manager as shown below.

Here, by entering “targets,” a list of available targets will appear. You will be able to see the ZYNQ PS (ARM Cortex-A9 Dual Core) and the PL (XC7Z010).

Then, perform the ARM Cortex-A9 On-chip Memory Read/Write test as follows:

Read the data at memory address 0x00001000. (You will see that the data stored at this address is 0.)

Write the value 0x12345678 to this address, and then read it again. (You can confirm that the data has been successfully written and read back correctly.)