Providing the Zynq PS clock and reset signals to the PL

Create a Vivado project and complete the PL design as follows.

Select “Tools – Create and Package New IP”.

Since the current project will be made into Package IP, Choose the Packaging Option “Package your current project”.

Specify where the IP will be created, and press Next.

Then, the packaging steps required for the IP Package appear.
Of these, only the necessary parts need to be set.

(1) Identification

Change ‘Vendor to a different name on “xilinx.com”.

(There’s nothing else to set.)

(2) Compatibility

Compatibility establishes an FPGA family that can be supported by that IP.
Make sure that ZYNQ is included in the family.

(3) File Groups

If you check the Synthesis and Simulation items in File Groups and package IP, the IP will include Synthesis and Simulation, which the current project includes.
However, in an another project, the IP is included as a component, and it would be Synthesized, Simulated, along with other components,
You don’t have to check the items above.

(4) Ports and Interfaces

You can check the clock, reset signals, and ports currently held by the IP project.
The IP is connected to other modules or IPs through the above signals and ports.

(5) Customization GUI

When the IP Packaging operation is completed, it can be confirmed that IP is generated with the above preview.

(6) Review and Package

Once you have finished setting up the IP Package, you can click “Package IP” to create the IP.

Create a separate Vivado project with the IP generated above as a component.
Then select “IP INTEGRATOR” – “Create Block Design” to create a block design.

The newly created IP will be called to Block Design and used, so you will need to add it in “Settings”.

Add IP in “Settings – IP – Repository” as follows.

If you specify a path where IP exists, a list of IPs in the path appears as follows.

It can be confirmed that the IP generated above exists in the specified path, and this IP can be added.

Then, you can call IP from the “Diagram” window of Block Design as follows.

The GUI of the called IP appears as follows.

IP’s “led[3:0]”, “sw[3:0]” ports are made External by selecting “Mouse R-click – Make External”.
(This is to connect with the MIO of ZYNQ specified by the XDC file.)

The IP’s “led[3:0]” port is then connected to an external port called “led_0[3:0]”,

If you look at Digilent’s Zybo Z7 XDC file, the Pin to which the LED element of the Zybo Z7 board is physically connected is M14, M15, G14, D18,

The names of the external ports are “led[0]”, “led[1]”, “led[2]”, and “led[3]”, respectively.

Therefore, the external port for the LED should be renamed from “led_0” to “led”.
(SW should be changed as well.)

Now, call ZYNQ IP (PS) to be used to supply clock and reset signals to IP.

And click Run Block Automation,

Create a Fixed_io and DDR.

Double-click on ZYNQ IP (PS), and uncheck things that are not used in this project.

The clock to be supplied to the LED Toggle IP (PL) is set as follows. (100MHz)

The clock and reset signals of the ZYNQ IP (PS) are then connected to the LED Toggle IP (PL).

Click Validate Design to verify that the block design you have worked on so far is valid.

When Design is valid, Integrate ZYNQ IP (PS) and LED Toggle IP (PL) into one wrapper file.

It can be seen that the wrapper file was created as follows.

Create a Bitstream of the corresponding Wrapper file.

When the Bit Stream generation is completed, resources used may be identified as follows.

It would be nice to program this BitStream directly into the FPGA, but ZYNQ-PS requires minimal Dummy Code to generate Clock, Reset signals.

Therefore, Export the Bit Stream to Vitis.

Select “Include bitstream” from the Export Hardware Platfrom.

Set the name and location of the Hardware Platform file to be exported to Vitis.

Once the hardware platform file has been exported, run Vitis IDE directly from Vivado.

In Vitis, click “Create Application Project” to create a Vistis project.

The following shows how to create a Vitis Application Project.
Press Next.

We will create a Vitis Application Project based on the Vivado project, So Add an XSA file (Hardware Platform).

Set the name of the Vitis Application Project, and press Next.

Press Next without setting it up.

For the Application Template, select “Empty Application(C)” and press Finish.

Add the C Source file to the generated Vitis Project.

The C Source file is named “main.c”.

For the operation of ZYNQ-PS, a minimum Dummy Code was written as follows.

Now, build that C project,

Launch to Hardware.

Then, it can be seen that Hardware Logic designed in ZYNQ PL receives a clock from PS and toggles the LED as follows.