Pages ListList viewHomeHomePortfolioDevelopZYNQ-7Z010 SOM B’d (Rev.A)STM32H743XIH6 SOM B’dMCU / FPGA / SOC Test Carrier B’d (Rev.A)Power Module (Type-A / Rev.B)HWSchematicPCB ArtworkAltium GuideCh 1. 시스템 / 프로젝트 환경설정Ch 2. 라이브러리 생성(Symbol, Footprint)Ch 3. 회로도 단축키Ch 4. Parameter SetCh 5. AnnotationCh 6. No ERC 설정Ch 7. PCB Doc에 회로도 불러오기Ch 8. PCB Doc 조작키 / 옵션 설정Ch 9. PCB Rule과 Constraint 설정하기Ch 10. PCB Board Outline DefinitionCh 11. Mechanical Layer에서 PCB Board Dimension 표시Ch 12. 개별 Rule에 대한 Net width 지정하기Ch 13. 다수의 Designator Silk 폰트를 한 번에 바꾸기Ch 14. PCB RoutingCh 15. Copper PourCh 16. Design Rule 설정Ch 17. Output Job File 생성기타 : Via Tent 설정하기FWSTM32 PeripheralsARM Cortex-M3/M4 Processor - 1ARM Cortex-M3/M4 Processor - 2ARM Cortex-M3/M4 Processor - 3STM32 HAL & Project ArchitectureUnderstanding STM32 HAL program flow with UART ExerciseClock & PLLGPIOI2CSPIUARTTimerCANDMASWFPGA / Adaptive SoCRTLAXI Specification of AMBAFPGACreating a Custom Non-AXI IPCreating a Custom AXI4-Lite IPHow to use a Custom AXI4-Lite IPHow to set up the ZYNQ SoC Development EnvironmentBRAM Controller AXI IPVitis Project Initial SetupFIFO Generator (Standard FIFO)FIFO Generator (First Word Fall Thru FIFO)Adaptive SoCUsage of PS region of ZYNQ ArchitectureProviding the Zynq PS clock and reset signals to the PLDailyPhoto20262024Haenggung-dongKota KinabaluMullae-dongMinato-Shinjuku, JapanAkihabara, JapanShibuya, JapanAsakusa, JapanAmi Art MuseumRoad 1950Kira Kira Studio2023Seoul Fashion Week 2023 FWProject MaybachNamsanSuseomSejong National ArboretumZen StudioSide Tempo SeongsuCrape Myrtle, Gunsan2022Sewoon Electronics PlazaDongtanOlympic ParkBukchon Hanok VillageDongtan Sairo Dulle-gil & MUJIEtcEtc Item FPGA / Adaptive SoCFPGACreating a Custom Non-AXI IPCreating a Custom AXI4-Lite IPHow to use a Custom AXI4-Lite IPHow to set up the ZYNQ SoC Development EnvironmentBRAM Controller AXI IPVitis Project Initial SetupFIFO Generator (Standard FIFO)FIFO Generator (First Word Fall Thru FIFO) FPGA